1. Field of the Invention
This invention relates to integrated circuit manufacture and more particularly to a method and device for removing a thin film from a wafer backside surface without requiring deposition and removal of photoresist and the problems associated therewith.
2. Description of the Relevant Art
The process steps of gettering a silicon substrate are well known. Gettering is used to remove lifetime reducing contaminants (usually heavy metals) from regions of the circuit where their presence would degrade device performance. Most all the transition metals, such as gold, copper, iron, titanium, nickel, etc., are reported as possible lifetime reducing contaminants. It is desirable to minimize the presence of such contaminants in the active regions in order to minimize reverse junction leakage, improve bipolar transistor gain, and increase refresh time in dynamic metal oxide silicon (MOS) memories.
Lifetime reducing contaminants (heavy metals) generally derive from at least a couple of sources. First, heavy metals often are found as part of the processing equipment, particularly where stainless steel delivery lines are used, and are naturally derived from that equipment during wafer fabrication. The wafer, unfortunately, receives the deleterious heavy metal ions during, for example, diffusion, chemical vapor deposition (CVD), sputtering, etc., steps. Second, heavy metal ions are often derived from the conductive material placed on the front and backside surfaces of the wafer. Frontside conductive material, generally referred to as "metalization", inherently uses heavy metal materials such as titanium and tungsten to enhance silicide growth and interconnect conductivity. Backside coating of gold is generally used to provide power supply conductivity to the wafer substrate, and also as an aid to bonding of the backside to the chip package. The front and backside heavy metal materials can easily migrate to the active regions to deleteriously effect circuit operations.
In order to sink or trap migration of heavy metal ions away from the active regions, gettering within the bulk silicon is necessary. There are two major forms of gettering: intrinsic gettering and extrinsic gettering. Intrinsic gettering involves forming gettering sites in the bulk of the silicon wafer generally near the active regions (near the front surface of the substrate). Intrinsic gettering generally includes an initial denuding step followed by a nucleation step, and then a precipitation step. Denudation, nucleation and precipitation, in combination, form lattice dislocations in the silicon bulk just below the active regions. The dislocations serve to trap heavy metal ions at the dislocation sites, away from the overlying active regions. Extrinsic gettering, on the other hand, generally involves gettering near the backside surface of the silicon substrate. There are several methods used to perform extrinsic gettering. Two common methods include (i) diffusing phosphorous into the backside surface of the wafer, and/or (ii) depositing polysilicon on the backside surface. Diffusion processes utilizing extrinsic gettering techniques such as phosphorous diffusion and polysilicon deposition is described in Runyan, et al., Semiconductor Integrated Circuit processing Technology, (Addision-Wesley publishing Co., 1990), pp. 428-442; and, DeBusk, et al., "Practical Gettering in High Temperature processing", Semiconductor International, (May 1992) (both of which are herein incorporated by reference).
It is the enhancement of processing steps used to produce extrinsic gettering that is relevant to the present application. Specifically, minimization and cost effectiveness for performing backside phosphorous diffusion and polysilicon deposition is of primary importance. Current backside phosphorous diffusion techniques involve placing semiconductor wafers on-edge in a wafer boat, and inserting the wafer boat into a diffusion furnace containing n-type dopants (i.e., phosphorous). Thus, the backside surface, as well as the frontside surface, receives phosphorous ions from the diffusion furnace. If polysilicon deposition is chosen as an extrinsic gettering technique, then said deposition occurs via low pressure CVD (LPCVD), wherein the back and front surfaces are both subjected to a silicon vapor source which precipitates as polycrystalline silicon on the front and backside surfaces.
From the above, it is understood that conventional techniques cannot selectively place extrinsic gettering materials (diffused phosphorous and deposited polysilicon) on only the backside surface absent a masking material such as photoresist on the frontside surface. This presents a problem. For example, if phosphorous is to be diffused into the backside surface, there must not be any barrier material, such as thick oxide, on the backside silicon surface. If non-native oxide (oxide generally greater than 70 Angstroms) pre-exists on the backside surface, then phosphorous ions cannot diffuse through that oxide and into the single crystal silicon material. Native oxide is generally less than 20 Angstroms. While it might be apparent that backside diffusion occur prior to thin film deposition (thin film deposition occurring on the front and backside surfaces simultaneously), it is noted that the phosphorous diffusion on the backside surface could harm circuit operation by phosphorous "outgassing" during subsequent thermal oxidation on the frontside surface. Thus, it is important that if phosphorous diffusion is the chosen extrinsic gettering technique, said diffusion must occur after gate oxide is formed on the frontside surface, so as to prevent phosphorous from outgassing into the frontside active regions underneath the gate oxide.
While phosphorous diffusion must occur after frontside oxide growth, it must occur prior to gold deposition on the backside surface and, more particular, before the wafer is subjected to high temperature cycles (i.e., anneal). Anneal steps generally occur in the wafer fabrication cycle after active region implant occurs. Anneal is used to activate the dopants placed in the active regions (source and drain regions) by subjecting the substrate to temperatures exceeding, for example, 1000.degree. C. Accordingly, if backside phosphorous diffusion is used, it must be performed while the backside surface embodies a bare single crystal silicon and before the single crystal silicon is subjected to anneal temperatures. Waiting until the backgrinding procedure would therefore be too late, since backgrinding step occurs after anneal.
From the above, it is understood that phosphorous diffusion, if used as the extrinsic gettering technique, must occur early in the wafer fabrication process, after gate oxide growth and polysilicon deposition. However, it is imperative that gate oxide and polysilicon be present on only the frontside surface so that the backside surface can receive the phosphorous ions. Conventional techniques used to achieve the above generally include growing gate oxide on the front and backside surface as well as thereafter depositing polysilicon on the front and backside surface. In order to remove the polysilicon and underlying gate oxide on the backside surface to prepare the backside surface for receiving gettering phosphorous ions, a masking material must be placed on only the frontside surface. The masking material, i.e., polymerized photoresist, prevents wet etch removal of the underlying polysilicon and gate oxide at the frontside surface while allowing backside removal of exposed polysilicon and gate oxide. The standard process therefore includes the steps of: (i) growing gate and/or tunnel oxide on the front and backside surface, (ii) depositing polysilicon on the front and backside surfaces, (iii) coating photoresist on the frontside surface only, (iv) typically subjecting the wafer to visual inspection to confirm photoresist coverage integrity, (v) polymerizing or baking/curing the photoresist placed on the frontside surface, (vi) removing exposed polysilicon on the backside surface only using a combination nitric acid and ammonium fluoride wet etch material, (vii) removing photoresist on the frontside surface using a ratio of sulfuric acid and hydrogen peroxide wet etch, (viii) removing gate oxide on the backside surface using a ratio of deionized water and hydrofluoric acid, and (x) removing photoresist residue (i.e., gross organics and metallics) using, for example, perchlorethylene and a combination of H.sub.2 O.sub.2 --NH.sub.4 O, H.sub.2 O.sub.2 --HCl and deionized water. The above steps of coating the front surface with photoresist, baking the photoresist, removing polysilicon, photoresist and oxide on the backside surface is not only time consuming, but also involves expensive, and numerous caustic materials. Additionally, use of photoresist during early stages of wafer processing may minimize the effectiveness of subsequent photolithography and selective polysilicon removal. Still further, any additional use of photoresist should be avoided in a cleanroom environment since photoresist, and the removal thereof, is a relatively "dirty" procedure which can compromise cleanroom integrity. The applicant of the present invention postulates that the cost involved in removal of backside polysilicon and gate oxide to be greater than $6.00 per wafer (assuming a five inch diameter wafer).
For reasons stated above, it would be advantageous to provide extrinsic gettering using backside phosphorous diffusion while avoiding use of the above steps of photoresist coat and removal on the front surface. It would be further advantageous to provide phosphorous deposition at the critical moment of wafer fabrication (i.e., at the time in which polysilicon is exposed at the front and backside surfaces, while the backside surface is absent gate oxide). It would be still further advantageous to provide not only phosphorous diffusion, but also polysilicon deposition on the backside surface subsequent to phosphorous diffusion. The combination of phosphorous diffusion and polysilicon deposition further enhances extrinsic gettering at the backside surface and thereby renders additional advantage in sinking lifetime reducing (heavy metal) contaminants away from the active regions on the front surface of the wafer.